EMC Question of the Week: April 13, 2020
An unmatched CMOS digital input can usually be modeled, to a first order, as
- a resistance of 50 to 100 Ω
- a resistance of 5 to 10 kΩ
- an inductance of 5 to 10 nH
- a capacitance of 5 to 10 pF
Answer
The correct answer is "d". CMOS inputs are primarily capacitive at the frequencies of greatest interest to EMC and signal integrity engineers. The transition time of digital signals with capacitive CMOS terminations has a time constant, τ = RC, where R is the source resistance and C is the termination capacitance. The capacitance of the circuit board trace connecting a source to a CMOS termination can also affect the transition time. For electrically short traces, we can usually add the trace capacitance to the termination capacitance to determine the transition time. If the trace propagation delay is longer than the transition time, it's generally necessary to match the termination impedance to the characteristic impedance of the signal trace to ensure good signal integrity.
For DC leakage current calculations, the capacitance is not important. At DC, the input impedance is a resistance that is typically well over 1 MΩ.
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