What People (and AI Agents) Get Wrong About Printed Circuit Board Decoupling

decoupling capacitor mounted on a printed circuit board through two closely spaced vias on the left side of the solder pads

Want to get a lot of reactions for your LinkedIn post? Just post some advice telling people how to do their printed circuit board decoupling. It doesn’t really matter what you say. People who agree with you will “like” your post. People who disagree will comment, and those comments will draw more “likes” and comments. AI agents will take notice, and pretty soon others will be posting the same information.

Models for successfully predicting the performance of the power distribution buses on printed circuit boards were developed more than 20 years ago. Yes, the models have continued to get better, and circuit board technologies have continued to evolve. Nevertheless, for most products, the basic advice governing the location and mounting of surface-mount decoupling capacitors is the same now as it was then.

I recently read a LinkedIn post that claimed a decoupling capacitor should be mounted within 3 mm of the active device pin in order to work at frequencies of 100 GHz and higher. Another person claimed that capacitors on the back side of a board sharing vias with a BGA component were the best source of high-frequency charge (because they were physically closest to the BGA). A third post recommended that both the power and ground pins of an active device should connect to the decoupling capacitor before connecting to the planes. All three posts included AI-generated graphics. All three posts had lots of “likes” and reposts. All three of them were utter nonsense.

The truth is that the steps necessary to provide adequate printed circuit board decoupling are highly dependent on the particular application. Decoupling for a 4-layer board in a kitchen appliance looks very different than decoupling for a 48-layer board controlling an autonomous vehicle. Appropriate design guidelines for power bus decoupling depend on many factors, including the target impedance, the board construction and stack-up, the component packaging, voltage levels, and how the power is distributed on the board.

Recurring advice in application notes and social media includes:

  • Locate decoupling capacitors as close to the active device power pins as possible.
  • Location is not important; spread the capacitors around.
  • Use capacitors with a low ESR.
  • Don’t use capacitors with a low ESR.
  • Use 0.1 μF capacitors for high-frequency decoupling.
  • Use multiple capacitor values with decade spacing for high-frequency decoupling.
  • Put a ferrite bead on the power input to noise-sensitive components.

Each of these guidelines may be exactly the right thing to do in a given situation. None of them is the right thing to do in every situation.

Printed circuit board decoupling is too broad a subject to be covered in a blog post. However, a tutorial on this website provides a pretty good overview of what the average product engineer needs to know. Of course, if you’re designing fast, power-hungry boards with target impedances measured in milliohms, you’re not relying on guidelines; you’re doing simulations.

By the way, in case you’re wondering why the three LinkedIn posts that I cited above are nonsense, I’ll try to explain.

  1. At 100 GHz and higher, no individual SMT capacitor mounted on the surface of a circuit board plays a significant role in reducing the power bus noise. The 3-mm distance is irrelevant.
  2. On a board with BGA components, small capacitors on the backside of the board connected to the vias associated with power and ground pins can be helpful. But at the highest frequencies (or in the first 100 ps of a sudden demand), they cannot compete with the power plane capacitance as a rapid source of charge. The capacitors with the lowest inductance connections to the planes will generally provide more current and contribute the most to meeting the target impedance at the highest frequencies.
  3. Finally, I’m not a big fan of EMC design guidelines in general. But one guideline that applies to virtually every high-frequency circuit board design with ground planes is, “Every ground pin of every component should connect directly to the ground plane (or planes).” Basically, if your board has a ground plane, it shouldn’t have any ground traces. Ground traces aren’t always a problem, but they’re almost never the right thing to do. I don’t care what you read on LinkedIn. 😊